|JR0181756 - Senior Logic Design Engineer|
Location: Phoenix, AZ
Employment Type: Full Time
Date Posted: 10/18/2021
Expire Date: 12/17/2021
Job Categories: Computers, Software, Engineering, Government and Policy, Healthcare, Practitioner and Technician, Information Technology, Internet/E-Commerce, Law Enforcement, and Security, Military, Research & Development, Medical, Web Technology, Energy / Utilities
JR0181756 - Senior Logic Design Engineer|
Come and join us! Intel is seeking highly qualified candidates to join our Datacenter and AI group (DC&AI) as a Senior Logic Design Engineer!
QAT (Quick Assist Technology) hardware design team enables Data Center Technology thru a set of scalable hardware accelerators, like lossless compression, network security like secure key establishment, IPSec, SSL/TLS, and firewall and data center virtualization technology like SRIOV, SIOV and SVM.
Within our QAT team, you will be a member of the CPM (Content Processing Module) front end design team, where you will work on RTL/DFX development and integration activities within the Custom Logic ASIC Engineering group in DCIA. You will play a key role in development and integration of CPM IP into Atom and Xeon based SOC. You will work with the IP/SoC integration teams and collaborate with the SoC design, validation, and emulation teams to ensure successful integration and validation of the CPM IP.
Responsibilities will include, but are not limited to:
- Perform logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs.
- Participate in the development of Architecture and Microarchitecture specifications for the Logic components.
- Provide IP integration support to SoC customers and represents RTL team.
- Implement RTL in System Verilog, validating the design, synthesizing the design, and closing timing.
- High-level Architecture through to the details of timing.
- Work with specifications at multiple levels, including the HAS and MAS (microarchitecture spec).
- Balance design trade-offs with modularity, scalability, DFX requirements, power, area, and performance.
The ideal candidate will have the following skills in addition to the qualifications listed below.
- Excellent analytical and problem-solving skills.
- Strong verbal/written communication skills.
- Effective team player with continuous learning mindset and experience working with external technology companies for combined development of IPs / SOCs.
- Experience balancing multiple tasks.
- Experience working in a fast-paced environment and have as much fun and growth as possible in the process.
- Work independently and at various levels of abstraction, with strong analytical skills.
In this position you will gain invaluable experience that will allow growth and expanded opportunities across Intel.
You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6 years of industry work experience, or
- Master's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4 years of industry work experience, or
- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 2 years of related work experience.
Minimum Required Qualifications:
- 4 plus years of experience with IP / ASIC design / validation in Front End processes including RTL development, functional and performance verification.
- 4 plus years of experience in design, development, and integration of design blocks (IP) for system-on-chip (SoC) components.
- 4 plus years of experience in Verilog and System Verilog based logic design.
- 4 plus years of experience in Perl and/or C++ programming.
- 3 plus years of experience in synthesis flow and timing closure.
- 2 plus years of experience in Formal Property Verification (FPV).
Additional Preferred Qualifications:
- Master's Degree or higher.
- Knowledge of considerations for performance, power and cost optimization.
- 3 plus years of experience in one/more of the following areas: PCIe, USB, AMBA standards (OCP, AXI, AHB etc.).
- 3 plus years of experience in SOC/IP physical design methodology and communication.Inside this Business Group
The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
Annual Salary Range for jobs which could be performed in US, Colorado:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here
USExperienced HireJR0181756PhoenixData Center Group