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JR0176375 - Design Automation Engineer
Company: Intel
Location: Hillsboro, OR
Employment Type: Full Time
Date Posted: 09/13/2021
Expire Date: 11/12/2021
Job Categories: Computers, Software, Engineering, Healthcare, Practitioner and Technician, Information Technology, Internet/E-Commerce, Military, Research & Development, Medical, Web Technology, Energy / Utilities
Job Description
JR0176375 - Design Automation Engineer

Product Enablement Solutions Group (PESG) is one of the key pillars, enabling Intel product design teams get to market faster with winning leadership products.

Following software engineering processes, the candidate develops state-of-the-art design tools, flows and methodologies (TFM) using Industry standard Electronic Design Automation (EDA) tools, to validate design methodologies on cutting edge process technologies.

Responsibilities of the role include, although not limited to:

  • IR Drop analysis (Static and Dynamic) TFM for SoC designs
  • Reliability Verification (RV) TFM for SoC designs
  • Power up analysis TFM for SoC designs
  • Creating TFM for die-die analysis

In addition to the qualifications listed below, the ideal candidate will also have:

  • Strong communication skills
  • Sense of urgency, strong organizational and follow up skills
  • Team player and willing to work in a collaborative environment
  • Logical problem-solving approach and the willing to clearly communicate the situation and proposed solution to the customer


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


Minimum Qualifications:
 

The candidate must have a Bachelor's degree in Electrical/Computer Engineering, Computer Science or related major with 3+ years of experience -OR- Master's degree in Electrical/Computer Engineering, Computer Science or related major with 2+ years of experience in the following:

  • Digital logic and CMOS circuit/layout VLSI design principles and techniques
  • Areas of standard cell physical layout, power-grid analysis, Timing analysis and Voltage drop effects
  • Layout extraction tools: StarRC or Quantus
  • Fusion complier or Innovus
  • Programming in scripting languages Perl, TCL and Python


Preferred Qualifications:

Experience in:

  • Semiconductor reliability physics and failure mechanisms
  • IR Drop/RV modeling tools: Voltus, Redhawk or Seascape
  • Cross functional/geo teams

Inside this Business Group

The Product Enablement Solutions Group (PESG) is a worldwide organization that delivers an end-to-end design system for development of IPs, Cores and SOCs. This business group partners with the Semiconductor, IP and EDA eco-systems and leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to deliver a world-class design system that powers Intel’s leadership products.



Other Locations

US, California, Folsom;US, California, Santa Clara



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USExperienced HireJR0176375HillsboroProduct Enablement Solutions Group
Contact Information
Company Name: Intel
Website: http://www.applytracking.com/x.aspx...
Company Description:

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